1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits and, more particularly, to integrated circuits including nonvolatile memory devices.
2. Description of the Related Art
Nonvolatile memory, such as, for example, flash memory, may be used in various storage devices, such as, for example, secure digital memory cards (SD cards), USB sticks, solid state drives (SSDs), and internal memory of various electronic devices, such as, for example, mobile phones, tablet computers, media players, etc. Further applications of nonvolatile memory include embedded systems, wherein nonvolatile memory blocks including nonvolatile memory are provided in addition to host logic devices and wherein the nonvolatile memory devices and the logic devices are physically and electrically integrated on a single substrate, for example, a single monolithic silicon substrate. Embedded systems including nonvolatile memory find applications in various fields, such as, for example, in automotive, industry and communication market segments. Integrating nonvolatile memory and logic circuitry on a single substrate may help to improve performance and reduce costs compared to solutions wherein nonvolatile memory and logic circuitry are provided on separate substrates, for example, due to an elimination of input/output buffers, design flexibility, lower power consumption and/or system-on-a-chip capability.
Types of nonvolatile memory cell architectures include one transistor cells (1T-cells) including a single gate, as well as split gate solutions such as 1.5 transistor (1.5T) and 2 transistor (2T) cells.
Examples of known nonvolatile memory cells include those described in U.S. Pat. Nos. 6,747,310 and 7,868,375.
Nonvolatile memory cells as described in U.S. Pat. Nos. 6,747,310 and 7,868,375 include a source region and a drain region that are formed in a semiconductor substrate. Between the source region and the drain region, a channel region is provided that is doped differently than the source region and the drain region. Over the channel region, a floating gate and a select gate are provided. Over the floating gate, a control gate is provided, and an erase gate is provided over the source region. The select gate, the floating gate, the control gate and the erase gate are electrically insulated from each other and from the source, drain and channel regions by electrically insulating materials. The floating gate may be surrounded by electrically insulating material so that it is electrically floating. The source region, the drain region, the select gate, the control gate and the erase gate may have respective electrical contacts connected thereto so that voltages may be applied to the source region, the drain region and the select, control and erase gates for performing operations of programming, erasing and reading the nonvolatile memory cell.
For programming the nonvolatile memory cell, voltages adapted for creating a relatively strong, substantially vertically oriented electrical field in the channel region between the select gate and the floating gate may be applied to the select and control gates and the source and drain regions, which may cause a hot electron injection into the floating gate so that the floating gate is electrically charged. Since the floating gate is electrically floating, the charge injected into the floating gate can remain in the floating gate and can create an electric field that acts on a portion of the channel region below the floating gate.
For reading data from the nonvolatile memory cell, a voltage may be applied between the source region and the drain region, and a voltage adapted for creating an electrically conductive channel below the select gate may be applied to the select gate. Due to the influence of the electric charge in the floating gate on the portion of the channel region below the floating gate, a current flowing between the source region and the drain region can be influenced by the electric charge of the floating gate. Thus, it can be determined if an electric charge has been injected into the floating gate by means of a programming operation.
For erasing the nonvolatile memory cell, a relatively high positive voltage may be applied to the erase gate, and a Fowler-Nordheim tunneling of electrons from the floating gate to the erase gate may be obtained. Thus, an electric charge injected into the floating gate in the programming of the nonvolatile memory cell can be removed from the floating gate. The select gate can provide a separation of the floating gate from the drain which may help to substantially avoid or at least reduce an over-erase phenomenon.
In nonvolatile memory cells, each of the select gate, the control gate, the erase gate and the floating gate may be formed of polysilicon, and silicon dioxide, silicon nitride and/or silicon oxynitride may be used for providing an electrical insulation between the select gate, the control gate, the erase gate and the floating gate and for providing an electrical insulation between the gates and the source, drain and channel regions of the nonvolatile memory cell.
In techniques for the formation of nonvolatile memory cells, each of the select gate, the control gate, the erase gate and the floating gate may be formed in a front-end-of-line (FEOL) module of a semiconductor manufacturing process, wherein techniques of furnace polysilicon deposition and chemical mechanical polishing (CMP) of polysilicon may be employed. Moreover, known techniques may include the use of sacrificial spacers and self-aligned reactive ion etching (RIE) may be employed in the formation of nonvolatile memory cells.
Nonvolatile memory cells and techniques for the formation thereof as described above may have issues associated therewith. Chemical mechanical polishing of polysilicon may be relatively expensive and may cause a relatively high amount of defects that can reduce the yield of the manufacturing process. Additionally, applying techniques as described above for small technology nodes such as, for example, the 28 nm technology node and below may have issues associated therewith which may be related to a sensitivity of the manufacturing process with respect to a topography of the semiconductor structure. Moreover, in semiconductor structures manufactured in accordance with small technology nodes such as the 28 nm technology node and below, it may be of advantage to encapsulate gates of logic transistors including high-k materials formed in the same semiconductor structure in silicon nitride after patterning the gate electrodes of the logic transistor, and the encapsulation of gate electrodes of logic transistors may be adversely affected by manufacturing processes such as chemical mechanical polishing of polysilicon.
The present disclosure provides methods for the formation of nonvolatile memory cells and semiconductor structures including nonvolatile memory cells which may help to substantially overcome or at least reduce some or all of the above-mentioned issues.